1. Technical Field
The present invention relates to a system and method for testing a large memory area during processor design verification and validation. More particularly, the present invention relates to a system and method for replicating a memory block throughout a main memory and modifying real addresses within a translation lookaside buffer (TLB) to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
Verifying and validating a processor using test cases typically includes three stages, which are 1) test case build stage, 2) test case execution stage, and 3) a validation and verification stage. A challenge found is that with an increasing demand for memory, processors reside on boards that include a large amount of memory. In test applications, however, a typical test case at any time only accesses a couple of pages of memory. As a result, a large number of test cases are required to cover large memory areas, which requires a large amount of build time.
What is needed, therefore, is a system and method for efficiently testing a large memory area.